1. Field of the Invention
This invention relates to a MOS semiconductor integrated circuit, and more particularly to a sub-booster circuit for raising an output voltage of a main booster circuit which generates a voltage higher than a power source voltage.
2. Description of the Related Art
In recent years, floating gate type nonvolatile semiconductor memories called EPROM and EEPROM have rapidly spread. Data can be electrically written into the EPROM and erased by application of ultraviolet rays. In the EEPROM, data can be written and erased electrically. This type of semiconductor memory includes, for example, a memory which utilizes the Fowler-Nordheim tunneling effect. In the memory utilizing the tunneling effect, electrons are injected into or discharged from the floating gate via the thin oxide film in the data write-in or erasing operation. In the data write-in or erasing operation, there is little current consumption. Therefore, the data write-in or erasing operation can be effected by using an output voltage of a booster circuit provided in the memory instead of externally applying a high voltage required for the data write-in or erasing operation. Thus, even if the booster circuit has a low current supplying ability, it can be used without any serious problem.
Recently, the circuit scale of the nonvolatile memory becomes large and the number of peripheral circuits (load circuits) to be supplied with a stepped-up voltage increases. Therefore, the load capacitance of the booster circuit increases, thereby making it necessary to take a long step-up time for raising an output voltage to a desired level. In the semiconductor integrated circuit, the load circuits to be supplied with an output voltage of the booster circuit are divided into a plurality of blocks and transfer gates are connected to input terminals of the respective blocks. The transfer gates are selectively activated by a control signal for selecting one of the blocks. An output voltage of the booster circuit is supplied to the load circuit block via the selected transfer gate. Thus, the load capacitance of the booster circuit is lowered, preventing the voltage step-up time from being increased.
As described above, in the case where the load circuits are divided into a plurality of blocks, it is necessary to apply a voltage higher than an output voltage of the booster circuit to the gate of the transfer gate. In other words, it is necessary to set the control signal for controlling the transfer gate higher than the output voltage of the booster circuit. This is because the voltage supplied to the load circuit block is lowered by the threshold voltage of the transfer gate. For this reason, a sub-booster circuit is used in addition to a main booster circuit in order to further raise a voltage which has been stepped up by the main booster circuit. An output voltage of the sub-booster circuit is higher than the output voltage of the main booster circuit by more than the threshold voltage of the transfer gate. The output voltage of the sub-booster circuit is supplied to the transfer gates to selectively activate the transfer gate. Since the transfer gate is selectively activated by a high voltage (equal to or higher than the sum of an output voltage of the main booster circuit and the threshold voltage of the transfer gate) of the sub-booster circuit, a voltage supplied from the booster circuit to the load circuit block will not be lowered by the threshold voltage of the transfer gate. Therefore, the output voltage of the booster circuit is efficiently supplied to the selected load circuit block.
With the use of the sub-booster circuit, the load capacitance of the main booster circuit can be lowered, thereby permitting a stepped-up voltage to be supplied to the load circuit in a brief time without lowering the output voltage of the main booster circuit. In this way, a high voltage used for writing or erasing data in a semiconductor memory can be generated in the semiconductor integrated circuit (such as a nonvolatile semiconductor memory).
Further, in a MOS semiconductor integrated circuit, a MOS transistor is used in the input stage of the load circuit, and a stepped-up voltage is applied to the gate of the MOS transistor. Therefore, a voltage supplied to the internal circuit of the load circuit is lowered by the threshold voltage of the input stage MOS transistor. For this reason, it is preferable to further raise an output voltage of the main booster circuit by means of the sub-booster circuit and supply it to the gate of the input stage MOS transistor even when the load circuits are not divided into a plurality of blocks.
For the reasons described above, it is required to use a highly efficient sub-booster circuit. However, the voltage step-up efficiency of the sub-booster circuit which is commonly used is not sufficiently high to further raise the output voltage of the main booster circuit, and therefore it is strongly required to develop the sub-booster circuit.